1. Field of the Invention
The present invention relates to disk controllers and particularly to a disk controller having a path obstruction determination function for determining controller modules (herein after called “CM”) to be obstructed and obstructing them in a way that minimizes effects on a system when an anomaly occurs in a data transfer path between a plurality of controller modules in a disk controller.
2. Description of the Related Art
FIG. 19 shows an example of a conventional disk controller. In FIG. 19, reference numeral 200 denotes a disk controller; reference numeral 201 each denotes a controller module (CM) which is responsible for data transfer control and error handling between a host processor and a disk device; reference numeral 202 denotes a path setting device having a switching function; reference numeral 203 denotes a channel adapter (CA) having an interface with the host processor; and reference numeral 204 denotes a device adapter having an interface with the disk device. The path setting device 202 is also called a Front End Router (FRT).
An I/O request from the host processor (not shown) to the disk device (not shown) is sent from a channel adapter 203 via a path setting device 202 to one of the plurality of CM 201 and then sent from such a CM 201 via a path setting device 202 to a device adapter 204, and thereby performing I/O to the disk device
In the conventional disk controller 200 as shown in FIG. 19, since channel adapters 203 and device adapters 204 are mounted on path setting devices 202 so that CMs 201, channel adapters 203, and device adapters 204 are each configured to be interconnected arbitrarily at any time, when a fault such as a failure occurs at any module, extent of impact of the fault can be localized in relatively easy way by obstructing and separating only a portion where the fault occurs.
In a disk controller described in Japanese Patent Laid-Open No. 2001-27972, each cluster which is composed of a plurality of channel adapter modules, a plurality of switch modules, and one cache module is supplied with power from different source, and each channel adapter or disk adapter module is able to set a plurality of path for transferring data from/to a particular cache module. The disk controller described in the above patent document also basically uses the same scheme as the disk controller illustrated in FIG. 19 with respect to obstructing and separating a module when a fault occurs.
FIG. 20 is a diagram for describing problems to be solved by the present invention. The inventor has been working on a development of new disk controller as shown in FIG. 20 that is different from the conventional disk controller. In FIG. 20, reference numerals 10, 11 each denotes a controller module (CM) which is responsible for data transfer control and error handling between a host processor and a disk device; reference numerals 70, 71 each denotes a path setting device having a switching function; reference numerals 40, 41 each denotes a channel adapter (CA) having an interface with the host processor; reference numerals 50, 51 each denotes a device interface (DI) having an interface with the disk device and corresponding to the device adapter shown in FIG. 19; and reference numerals 60, 61 each denotes a transfer circuit which is composed of a DMA chip and the like for transferring data.
The disk controller shown in FIG. 20 is greatly different from the conventional disk controller 200 as shown in FIG. 19 in that there are the channel adapters as host interfaces and the device interfaces as interfaces with the disk devices in the CMs 10, 11. This is intended to simplify a path for transferring data from the host processor to the disk device via the CM 10 or 11 as much as possible and thereby facilitating control, as well as to achieve cost reduction of the CM including channel adapters and device interfaces.
In addition, data transfer between the CM 10 and the CM 11 is performed via the transfer circuit 60, 61 and the path setting device 70 or 71 as required.
Thus, in the disk controller illustrated in FIG. 20, since the channel adapters and the device interfaces exist in the CM 10, 11, there is a problem that, when the CM 11 is obstructed for example, channel adapters 41 and device interfaces 51 of the CM 11 are also obstructed and therefore its effect on the system becomes increased. As used herein, obstruction means a state in which a particular part such as a device and a circuit is unavailable.